Multiprocessor Performability Analysis

TitleMultiprocessor Performability Analysis
Publication TypeJournal Article
Year of Publication1993
AuthorsN Lopez-Benitez, and KS Trivedi
JournalIeee Transactions on Reliability
Volume42
Issue4
Start Page579
Pagination579 - 587
Date Published01/1993
Abstract

Performability models of multiprocessor systems and their evaluation are presented. Two cases in which hierarchical modeling is applied are examined. 1. Models are developed to analyze the behavior of processor arrays of various sizes in the presence of permanent, transient, intermittent, and near-coincident faults. Models can be generated for typical reconfiguration schemes that consider the failures of several types of components (detailed modeling). These models consider a survivability factor derived in terms of the physical distribution of faulty components. Capacity-based reward rates are then used to derive overall performability measures. 2. Queueing network models are solved to derive performance measures that are used as reward rates within an overall Markov failure-repair model of bus-based multiprocessor systems. Several configurations are compared in terms of their performability. In both cases, Markov models are generated using MGRE and solved using SHARPE. The analysis, particularly for case 2, is by no means exhaustive as several parameters are involved in the overall model. However, the hierarchical models shown, combined with the use of diverse tools such as MGRE & SHARPE, facilitate the analysis of large systems in various environments. The models can be fine-tuned according to specific applications and performance measures. © 1993 IEEE

DOI10.1109/24.273586
Short TitleIeee Transactions on Reliability